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Annotation 7655714852108

Access value to which p points with dereference operator *

printf("%d", *p); // prints 42
*p = 12;
printf("%d", i); // prints 12

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Annotation 7656406912268

#has-images

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Annotation 7656461700364

#has-images

Improving one aspect of computer does not yield proportional

improvement in overall performance

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Annotation 7656587005196

[RISC] Arithmetic instructions use register operands

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Annotation 7656588578060

[RISC-V] 32 general purpose registers x0 to x31

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Annotation 7656590150924

[RISC] [Registers] Used for frequently accessed data

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Procedure call instructions

Procedure call: jump-and-link instruction

jal x1, ProcedureLabel

Executed by caller
Puts address of instruction after this one in x1 (ra) (return address)
Jumps to target address of ProcedureLabel

Procedure return: jump-and-link register instruction

jalr x0, 0(x1)

Executed by callee
Like jal, but jumps to 0 + address in x1 (ra)
No return address (x0 cannot be changed)
Can also be used for unconditional jumps

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Annotation 7657117060364

#has-images

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Flashcard 7657371340044

Question

A structure is [...]

struct point
{
  int x;
  int y;
};

Answer

a new type

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Structure is collection of variables that belong together A structure is a new type Example: struct point { int x; int y; };

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Flashcard 7657386020108

Question

[...] processor
Designed for parallelism and high throughput at expense of higher latency and lower single-thread performance

Answer

Manycore

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Manycore processor Designed for parallelism and high throughput at expense of higher latency and lower single-thread performance

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Flashcard 7657402797324

Question

[...]

High-level view of complete computing system
Example: For a desktop computer, it includes the components CPU, memory, I/O, and interconnection paths between them System architecture

Answer

System architecture

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System architecture High-level view of complete computing system Example: For a desktop computer, it includes the components CPU, memory, I/O, and interconnection paths between them System architecture </s

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Flashcard 7657672805644

Tags

#has-images

Question

[...]
Quotient of two performance results, where denominator is baseline performance:

Answer

Relative performance

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Relative performance Quotient of two performance results, where denominator is baseline performance:

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Flashcard 7657674378508

Tags

#has-images

Question

Relative performance

[...]

Answer

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Relative performance Quotient of two performance results, where denominator is baseline performance:

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Flashcard 7657676737804

Question

Tell compiler about [...]:

–I<path/to/dir1> –I<path/to/dir2>

Answer

additional search directories for header files

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Tell compiler about additional search directories for header files: –I<path/to/dir1> –I<path/to/dir2>

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Flashcard 7657678310668

Question

Tell compiler about additional search directories for header files:

[...]

Answer

–I<path/to/dir1> –I<path/to/dir2>

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Tell compiler about additional search directories for header files: –I<path/to/dir1> –I<path/to/dir2>

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Flashcard 7657679883532

Question

[C] [...] defines new name for a type

Answer

typedef

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typedef defines new name for a type typedef int Integer; Integer i = 3;

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Flashcard 7657681456396

Question

[C] typedef defines [...]

Answer

new name for a type

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typedef defines new name for a type typedef int Integer; Integer i = 3;

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Flashcard 7657683815692

Question

typedef defines new name for a type

[...]

Answer

typedef int Integer; Integer i = 3;

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typedef defines new name for a type typedef int Integer; Integer i = 3;

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Annotation 7657685388556

Variable declaration of a struct
struct point a;

Variable declaration with initialization
struct point b= {1, 2};

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Variable declaration of a struct struct point a; Variable declaration with initialization struct point b= {1, 2}; Access to members through member access operator . struct point p; p.x= 1; p.y= 2;

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Annotation 7657686961420

member access operator .

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Parent (intermediate) annotation

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Flashcard 7657688534284

Question

Since 2002, uniprocessor performance improvement dropped
Further performance improvements by [...]

Answer

placing multiple processors on single die (multi-core architecture)

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Multicore Since 2002, uniprocessor performance improvement dropped Further performance improvements by placing multiple processors on single die (multi-core architecture) Initially called on-chip or single-chip multiprocessing Cores often share resources (e.g., caches, memory, I/O) Limited by memory bandwidth Leverages design investment by replicating it

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Flashcard 7657690107148

Question

Multicore

Since [...], uniprocessor performance improvement dropped
Further performance improvements by placing multiple processors on single die (multi-core architecture)
Initially called on-chip or single-chip multiprocessing
- Cores often share resources (e.g., caches, memory, I/O)
Limited by memory bandwidth
Leverages design investment by replicating it

Answer

2002

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Flashcard 7657692466444

Question

[...] 32 general purpose registers x0 to x31

Answer

[RISC-V]

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[RISC-V] 32 general purpose registers x0 to x31

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Flashcard 7657694039308

Question

[RISC-V] [...] general purpose registers x0 to x31

Answer

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[RISC-V] 32 general purpose registers x0 to x31

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Flashcard 7657695612172

Question

[RISC-V] 32 [...] registers x0 to x31

Answer

general purpose

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[RISC-V] 32 general purpose registers x0 to x31

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Flashcard 7657697185036

Question

[RISC-V] 32 general purpose registers [...]

Answer

x0 to x31

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[RISC-V] 32 general purpose registers x0 to x31

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Flashcard 7657698757900

Question

[RISC-V] Memory is [...] addressed

Answer

byte

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ory operands Main memory used for composite data Arrays, structures, dynamic data For arithmetic operations Load values from memory into registers Store result from register to memory Memory is byte addressed Each address identifies 8-bit byte

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Flashcard 7657700330764

Question

Main memory used for [...] data

Answer

composite

(i.e. Arrays, structures, dynamic data)

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Memory operands Main memory used for composite data Arrays, structures, dynamic data For arithmetic operations Load values from memory into registers Store result from register to memory Memory is byte addressed Each address identif

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Flashcard 7657701903628

Question

Memory operands

Main memory used for composite data
- [...]
For arithmetic operations
- Load values from memory into registers
- Store result from register to memory
Memory is byte addressed
- Each address identifies 8-bit byte

Answer

Arrays, structures, dynamic data

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Flashcard 7657703476492

Question

Arrays of 3 point structures (malloc)

struct point a[3];

[...]

Answer

struct point* b = malloc(sizeof(struct point) * 3);

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Arrays of 3 point structures struct point a[3]; struct point* b = malloc(sizeof(struct point) * 3);

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Flashcard 7657705835788

Question

Arrays of 3 point structures (normal)

[...]

struct point* b = malloc(sizeof(struct point)  * 3);

Answer

struct point a[3];

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Arrays of 3 point structures struct point a[3]; struct point* b = malloc(sizeof(struct point) * 3);

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Flashcard 7657708195084

Question

Sign extension

same number, more bits
Replicate [...] to the left
RISC-V:
- lb (load byte): sign-extend loaded byte (byte interpreted as 2's-complement)
- lbu (load byte unsigned): zero-extend loaded byte
- addi (add immediate): sign-extend 12-bit immediate (immediate interpreted as 2's complement)

Answer

sign bit

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Sign extension same number, more bits Replicate sign bit to the left RISC-V: lb (load byte): sign-extend loaded byte (byte interpreted as 2's-complement) lbu (load byte unsigned): zero-extend loaded byte addi (add immediate): sign-extend 12-b

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Flashcard 7657709767948

Question

Number of clock cycles for program depends on:

[...]
- Determined by ISA and compiler
Average number of clock cycles per instruction (CPI)
- Determined by CPU hardware
- Usually, different instructions have different CPI
- CPI of a program (code sequence) depends on instructions executed (instruction mix)

Answer

Number of instructions executed (instruction count)

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From clock cycles to instruction count and CPI Number of clock cycles for program depends on: Number of instructions executed (instruction count) Determined by ISA and compiler Average number of clock cycles per instruction (CPI) Determined by CPU hardware Usually, different instructions have different CPI CPI of a program (code

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Flashcard 7657711340812

Question

Number of clock cycles for program depends on:

Number of instructions executed (instruction count)
- Determined by ISA and compiler
[...]
- Determined by CPU hardware

Answer

Average number of clock cycles per instruction (CPI)

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Flashcard 7657712913676

Question

From clock cycles to instruction count and CPI

Number of clock cycles for program depends on:

Number of instructions executed (instruction count)
- Determined by [...]
Average number of clock cycles per instruction (CPI)
- Determined by CPU hardware
- Usually, different instructions have different CPI
- CPI of a program (code sequence) depends on instructions executed (instruction mix)

Answer

ISA and compiler

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Flashcard 7657714486540

Question

From clock cycles to instruction count and CPI

Number of clock cycles for program depends on:

Number of instructions executed (instruction count)
- Determined by ISA and compiler
Average number of clock cycles per instruction (CPI)
- Determined by [...]
- Usually, different instructions have different CPI
- CPI of a program (code sequence) depends on instructions executed (instruction mix)

Answer

CPU hardware

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ber of clock cycles for program depends on: Number of instructions executed (instruction count) Determined by ISA and compiler Average number of clock cycles per instruction (CPI) Determined by CPU hardware Usually, different instructions have different CPI CPI of a program (code sequence) depends on instructions executed (instruction mix)

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Flashcard 7657716059404

Question

Was sind Registerfenster?

Registerfenster sollen das Lokalhalten von Daten unterstützen. Typische RISC Prozessoren wie die Berkeley RISC besitzen weit über 100 Register, von denen aber immer nur 32 für sichtbar sind:

R0...R9 globale Register
R10...R15 Ausgaberegister
R16...R25 lokale Register
R26...R31 Eingaberegister

Die Idee ist nun, daß die ersten 10 Register von allen Prozeduren gesehen werden. Die Restlichen von R10 bis R31 sind [...] zugeordnet. Falls nun eine Prozedur eine andere aufruft, wird nur das "Fenster" auf einen freien Registerbereich umgeschaltet. So müssen die Register nicht neu aus dem Speicher geladen werden und es wird dadurch viel Zeit gespart. Normalerweise überlappen sich die einzelnen Fenster um einige Register, um somit gleich eine effiziente Möglichkeit der Parameterweitergabe zu bieten.

Answer

jeweils nur einer Prozedur

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0...R15 Ausgaberegister R16...R25 lokale Register R26...R31 Eingaberegister Die Idee ist nun, daß die ersten 10 Register von allen Prozeduren gesehen werden. Die Restlichen von R10 bis R31 sind jeweils nur einer Prozedur zugeordnet. Falls nun eine Prozedur eine andere aufruft, wird nur das "Fenster" auf einen freien Registerbereich umgeschaltet. So müssen die Register nicht neu aus dem Speicher geladen

Original toplevel document

Grundprinzipien der Rechnerarchitektur
er liegen, werden in kontinuierlicher Folge abgespeichert. Gepaart mit multiple branch prediction können mehrere zusammenhängende Basisblöcke parallel gefetched werden. (ergibt hohe issue rate) Kapitel 5 - Risc Wie berechnet sich die Prozessorleistung? Die Prozessorleistung ist umgekehrt proportional zur Ausführungszeit eines Algorithmus und wird aus folgenden drei Parametern ermittelt: Worum geht es im Besonderen bei einer Risc-Architektur? RISC Architekturen sind darauf aus, die Cycles Per Instruction zu minimieren. Das heißt, es wird versucht alle Befehle mit so wenig wie möglich Takten auszuführen. Welche architektonischen Möglichkeiten gibt es zur Veringerung der CPI? Piplining ergibt eine CPI > 1, andere Techniken wie Superskalarität und VLIW's haben Ausführungszeiten von kleiner als eins. Kombiniert ergeben beide Ansätze eine nahezuhe Ausführung von einem Befehl pro Takt. Desweiteren ermöglicht der kleine Befehlssatz von RISC eine festverdrahtete Steuereinheit, anstatt von Mikroprogrammen, welche höhere Taktzahlen pro Befehl mit sich bringen. Desweiteren muss bei einem Risc-Befehl nicht der Op-Code dekodiert werden, um herauszufinden, wie der Befehl zu entschlüsseln ist, da alle Befehle die gleiche Struktur besitzen. Auf welche vier Merkmale wird beim RISC-Design-Entwurf besonders geachtet? einfache Maschinenbefehle und Adressierungsarten mit einheitlichen Befehlsformat große und universelle Registersätze, für schnelle Variablenverarbeitung und größere Optimiermöglichkeiten für Compiler Verzahnung von Compiler und Architektur zur Bereitstellung von optimierenden Compilern Optimierte VLSI-Chipfläche durch platzsparende Steuerwerke schafft mehr Platz für Optimiertechniken wie Pipelining,Branch-Prediction oder Superskalarität Techniken zur Ablaufparallelisierung für RISC-Kerne Parallelität von einzelnen Befehlsphasen durch Pipelining Parallelität von ganzen Befehlen durch Superskalartechnik und VLIW Parallelität von Kodefäden durch Multithreading (programmierte Parallelität) oder Multiskalarität (Hardwarethreaderkennung) Parallelität von Befehlen unabhängiger Algorithmen (Multiprozessorsysteme) Pentium 4 Prozessor Kern Load / Store Architektur und Lokalhalten von Daten Da Speicherzugriffe in Pipelines starke Konflikte hervorrufen, gibt es bei RISC-Befehlssätzen nur eine einzige Möglichkeit mit LOAD bzw. STORE auf den Speicher zuzugreifen. So werden Registerzugriffe von Speicherzugriffen getrennt. Da Speicherzugriffe bekanntermaßen immer sehr viel Zeit kosten, versucht man diese so weit wie möglich zu vermeiden. Dies Erreicht man durch Lokalhalten von Daten, bzw. das Arbeiten auf den Registern. Was sind Registerfenster? Registerfenster sollen das Lokalhalten von Daten unterstützen. Typische RISC Prozessoren wie die Berkeley RISC besitzen weit über 100 Register, von denen aber immer nur 32 für sichtbar sind: R0...R9 globale Register R10...R15 Ausgaberegister R16...R25 lokale Register R26...R31 Eingaberegister Die Idee ist nun, daß die ersten 10 Register von allen Prozeduren gesehen werden. Die Restlichen von R10 bis R31 sind jeweils nur einer Prozedur zugeordnet. Falls nun eine Prozedur eine andere aufruft, wird nur das "Fenster" auf einen freien Registerbereich umgeschaltet. So müssen die Register nicht neu aus dem Speicher geladen werden und es wird dadurch viel Zeit gespart. Normalerweise überlappen sich die einzelnen Fenster um einige Register, um somit gleich eine effiziente Möglichkeit der Parameterweitergabe zu bieten. Was passiert wenn alle Registerfenster voll sind? Bei unserem Beispiel mit 138 Registern sind nach sieben Prozeduraufrufen alle Register gefüllt. Um ein Überlaufen zu vermeiden, wird das Register als Ringregister organisiert. Sind alle Registerfenster voll, wird das Älteste in den Speicher ausgelagert, was von sogenannten Trap-Routinen erledigt wird. Was sind Superpipelines? Superpipes vereinen Arithmetisches und Befehlspipelining. Arithmetisches Pipelining ist sogenanntes Funktionspipelining, bei dem einzelne Phasen eines Befehles in einer Pipeline-Form organisiert werden. Bei Instruction Pipelining wird die Abarbeitung eines gesamten Befehls in einer Pipeline organisiert. Zusammenfassung Risc Einfachere Befehlssätze mit ca. 40-80 Befehlstypen Einfachere Steuerung durch die Hardware ohne Mikroprogramme Effizientere Pipelines durch gleichlange, eintaktige Stufen Befehle können meist in einem Takt ausgeführt werden Datenzugriffe nur durch Load und Store um Speicherzugriffe zu vermeiden Mehr Register und Optimierung des Befehlssatzes durch Compiler Typische Riscsysteme haben eine hartverdrahtete Steuereinheit und somit keinen Mikrocodespeicher. Der Pentium ist ein "hybrid"-System mit RISC Kern. Dabei werden komplexe CISC Befehle durch ein Mikroprogramm in RISC zerlegt und im Kern ausgeführt. Die einfachen Befehle werden direkt im RISC Kern in einem einzigen Datenzyklus ausgeführt. Alle wichtigen elementaren (Risc) Befehle werden direkt von Level 0 ( der Hardware ) ausgeführt und somit nicht via Mikroinstruktionen interpretiert. Dies ist ein Vorteil von reinen RISC Systemen, welche diese Interpretationsebene zwischen Hardware und ISA (Instruction Set Architecture) Ebene nicht durchlaufen müssen. Mikroinstruktionen steuern den Datenweg für einen Zyklus. Sie enthält alle notwendigen Bit-Belegungen für ALU, MEM, Register etc., um einen Zyklus abarbeiten lassen zu können. Die Adresse der nächsten Mikroinstruktion wird ebenso mit codiert, wie die Art und Weise des Aufrufes. Die Mikroinstruktionen werden in einem Steuerspeicher gehalten, welcher das jeweilige Mikroprogramm enthält. Der Steuerspeicher muss die Mikroinstruktionen nicht in geordneter oder sequentieller Folge enthalten, wie es beim Hauptspeicher der Fall ist. Es kann jede Instruktion einen Verweis auf die Nächste enthalten. Sprünge sind einfach möglich. Angewandt wird dies in Form von Opcodes, welche nichts anderes als Adressen auf Mikroinstruktionen im Steuerspeicher sind. Kapitel 6 - Pipelining Wozu dient Pipelining? Pipelining soll es ermöglichen Befehle überlappt auszuführen. Dazu sind ein einheitliches Befehlsformat fester Länge Grundlage. Deshalb wer

Flashcard 7657717632268

Question

Was sind Registerfenster?

Registerfenster sollen das Lokalhalten von Daten unterstützen. Typische RISC Prozessoren wie die Berkeley RISC besitzen weit über 100 Register, von denen aber [...]:

R0...R9 globale Register
R10...R15 Ausgaberegister
R16...R25 lokale Register
R26...R31 Eingaberegister

Die Idee ist nun, daß die ersten 10 Register von allen Prozeduren gesehen werden. Die Restlichen von R10 bis R31 sind jeweils nur einer Prozedur zugeordnet. Falls nun eine Prozedur eine andere aufruft, wird nur das "Fenster" auf einen freien Registerbereich umgeschaltet. So müssen die Register nicht neu aus dem Speicher geladen werden und es wird dadurch viel Zeit gespart. Normalerweise überlappen sich die einzelnen Fenster um einige Register, um somit gleich eine effiziente Möglichkeit der Parameterweitergabe zu bieten.

Answer

immer nur 32 für sichtbar sind

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n> Was sind Registerfenster? Registerfenster sollen das Lokalhalten von Daten unterstützen. Typische RISC Prozessoren wie die Berkeley RISC besitzen weit über 100 Register, von denen aber immer nur 32 für sichtbar sind: R0...R9 globale Register R10...R15 Ausgaberegister R16...R25 lokale Register R26...R31 Eingaberegister Die Idee ist nun, daß die ersten 10 Register von allen Prozeduren gesehen werden.

Original toplevel document

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Question

Was sind Registerfenster?

Registerfenster sollen das Lokalhalten von Daten unterstützen. Typische RISC Prozessoren wie die Berkeley RISC besitzen weit über 100 Register, von denen aber immer nur 32 für sichtbar sind:

R0...R9 globale Register
R10...R15 Ausgaberegister
R16...R25 lokale Register
R26...R31 Eingaberegister

Die Idee ist nun, daß die ersten 10 Register von allen Prozeduren gesehen werden. Die Restlichen von R10 bis R31 sind jeweils nur einer Prozedur zugeordnet. Falls nun eine Prozedur eine andere aufruft, wird nur das "Fenster" auf einen freien Registerbereich umgeschaltet. So müssen die Register [...] und es wird dadurch viel Zeit gespart. Normalerweise überlappen sich die einzelnen Fenster um einige Register, um somit gleich eine effiziente Möglichkeit der Parameterweitergabe zu bieten.

Answer

nicht neu aus dem Speicher geladen werden

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R10 bis R31 sind jeweils nur einer Prozedur zugeordnet. Falls nun eine Prozedur eine andere aufruft, wird nur das "Fenster" auf einen freien Registerbereich umgeschaltet. So müssen die Register nicht neu aus dem Speicher geladen werden und es wird dadurch viel Zeit gespart. Normalerweise überlappen sich die einzelnen Fenster um einige Register, um somit gleich eine effiziente Möglichkeit der Parameterweitergabe zu bie

Original toplevel document

Annotation 7657720777996

Normalerweise überlappen sich die einzelnen Fenster um einige Register, um somit gleich eine effiziente Möglichkeit der Parameterweitergabe zu bieten.

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ine andere aufruft, wird nur das "Fenster" auf einen freien Registerbereich umgeschaltet. So müssen die Register nicht neu aus dem Speicher geladen werden und es wird dadurch viel Zeit gespart. Normalerweise überlappen sich die einzelnen Fenster um einige Register, um somit gleich eine effiziente Möglichkeit der Parameterweitergabe zu bieten.

Original toplevel document

Annotation 7657722350860

Falls nun eine Prozedur eine andere aufruft, wird nur das "Fenster" auf einen freien Registerbereich umgeschaltet.

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e Register R26...R31 Eingaberegister Die Idee ist nun, daß die ersten 10 Register von allen Prozeduren gesehen werden. Die Restlichen von R10 bis R31 sind jeweils nur einer Prozedur zugeordnet. Falls nun eine Prozedur eine andere aufruft, wird nur das "Fenster" auf einen freien Registerbereich umgeschaltet. So müssen die Register nicht neu aus dem Speicher geladen werden und es wird dadurch viel Zeit gespart. Normalerweise überlappen sich die einzelnen Fenster um einige Register, um somit

Original toplevel document

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Question

Passing arrays as parameters

Pass [...] of first array element

#include <stdio.h>

void foo(int*a)
{
    printf("%p\n", a);  
}
 
int main()
{
    int a[10];
    printf("%p\n", a);  
    foo(a);
}

Answer

address

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Passing arrays as parameters Pass address of first array element``` #include <stdio.h> void foo(int*a) { printf("%p\n", a); } int main() { int a[10]; printf("%p\n", a); foo(a); }

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Question

What does this do?

void free(void* p); // declared in stdlib.h

Answer

Frees memory of passed pointer

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r must take care to free memory Program may run out of memory when repeated allocations are not freed Memory management is source of many errors in C void free(void* p); // declared in stdlib.h Frees memory of passed pointer

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Question

[C] Which function frees the memory of a passed pointer?

Answer

void free(void* p); // declared in stdlib.h

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(malloc) not automatically freed ➜ Programmer must take care to free memory Program may run out of memory when repeated allocations are not freed Memory management is source of many errors in C void free(void* p); // declared in stdlib.h Frees memory of passed pointer

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Question

[C] Where is free() declared?

Answer

stdlib.h

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Programmer must take care to free memory Program may run out of memory when repeated allocations are not freed Memory management is source of many errors in C void free(void* p); // declared in stdlib.h Frees memory of passed pointer

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Question

Is malloc'ed memory automatically freed?

Answer

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Dynamically allocated memory (malloc) not automatically freed ➜ Programmer must take care to free memory Program may run out of memory when repeated allocations are not freed Memory management is source of many errors in C void

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Question

Pipelining bedeutet, Befehle [...] auszuführen.

Answer

überlappt

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Pipelining bedeutet, Befehle überlappt auszuführen.

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Grundprinzipien der Rechnerarchitektur
einen Verweis auf die Nächste enthalten. Sprünge sind einfach möglich. Angewandt wird dies in Form von Opcodes, welche nichts anderes als Adressen auf Mikroinstruktionen im Steuerspeicher sind. Kapitel 6 - Pipelining Wozu dient Pipelining? Pipelining soll es ermöglichen Befehle überlappt auszuführen. Dazu sind ein einheitliches Befehlsformat fester Länge Grundlage. Deshalb werden werden nur auf Register getätigt. Für Speicheroperationen wird die LOAD / STORE Philosophie verfolgt, um langsame Hauptspeicherzugriffe zu minimieren. Was ist Voraussetzung für Pipelining? Die Befehlsverarbeitungsphase muss sich in mehrere voneinander unabhängige Phasen unterteilen lassen. Die einfachste Form einer Pipeline ist die 5-stufige mit folgenden Phasen: Befehl holen Befehl dekodieren Befehl ausführen Auf Speicher zugreifen Ergebnis in Register schreiben Moderene CPU's haben weitaus komplexere Pipelines, in denen die einzelnen Stufen wiederrum in mehrere sich überlappende Phasen aufgeteilt werden. Der allgemeine Aufbau einer (fünfstufigen) Pipeline Um Parallelität in der Befehlsausführungsphase zu erreichen, wird der Datenpfad so konstruiert, daß folgende (hier fünf) Phasen unabhänig voneinander arbeiten können. Nur so ist es möglich eine verzahnte Abarbeitung mehrerer Befehle zu erreichen. Abb.: Die Piplelinestufen Somit wird ,nachdem eine Pipeline gefüllt ist, im Optimalfall pro Takt ein Befehl fertig. (CPI = 1) Welche Pipeline-Konflikte müssen behandelt werden? Datenabhängigkeiten (Data Hazards) Sind logische Abhängigkeiten, welche eine verzögerte Abarbeitung erfordern, weil z.B. ein Folgebefehl auf ein Ergebnis eines anderen Befehles warten muss. Jump- / Branchverzögerungen (Control Hazards) Bei Sprungbefehlen liegt oft das Sprungziel nach der Dekodieung noch nicht fest. Somit müssen Techniken eingesetzt werden um diese Wartezeiten zu minimieren. (Branch Prediction) Ressourcenkonflikte (Structural Hazards) Bei bestimmten Befehlskombinationen ist es unter Umständen möglich, daß ein Teilwerk seine Arbeit wiederholen muss. Solche Ressourcenkonflikte treten dann auf, wenn nicht jeder Teilphase völlig unabhängige Teilwerke zugeordnet sind. Ein Beispiel ist z.B. ein zeitgleicher Lesezugriff eines LOAD/STORE Befehles, welcher sich zwangsweise mit einem eventuellen MEM ACCESS eines anderen Befehles überschneidet. Abhilfe können hier Dual-Port RAM, Havard-Architektur oder getrennte Code- und Datencaches schaffen. Welche drei verschiedenen Datenabhängigkeiten gibt es? RAW, WAW und WAR-Konflikte sind Datenabnhänigkeiten, welche in Pipelines auftreten können. Dabei ist das RAW-Problem für Pipelines typisch. WAR Konflikte treten eher bei Out-Of-Order Execution auf. Um Read-After-Write Konflikte aufzulösen, gibt es verschiedene Ansätze wie Softwarelösungen ( Compileroptimierung), Scoreboarding (zentrale Steuerlogik) und Forwarding (zusätzlicher Datenpfad). Was ist Forwarding? Beim Forwarding wird ein Bypass eingerichtet, welcher ein Ergebniss einer Operation schon einem Folgebefehl zur Verfügung stellt, bevor es überhaupt in ein Register geschrieben wurde. Aber trotz Load-Forwarding hat ein Ladebefehl eine Verzögerung, welche nicht gänzlich eliminiert werden kann. In diesem Fall kann die Delayed-Load Technik oder auch eine Befehlsumordnung Anhilfe schaffen. Was ist die Delayed Load-Technik? Bei der Delayed Load-Technik wird die Verzögerung nach einem LOAD Befehl als architektonisches Merkmal angesehn und den Compilerbauern offengelegt. Diese können nun durch Befehlsumordnungen versuchen, nach einem LOAD-Befehl einen datenunabhängigen Befehl einzufügen, um den Slot zu füllen. Zusammenfassung Pipelining Pipelines werden in allen modernen CPUs benutzt. Die UltraSparc2 hat neun und der P2 zwölf Stufen. Der Intel Pentium Itanium weißt eine 20 stufige Superpinepline (pipeline in der sich einzelne Stufen überlappen können) auf! Pipes werden heutzutage in Kombination mit der Superskalartechnik verwendet, um höchste Effizienz und Parallelverarbeitung gewährleisten zu können. Die fünf grundlegenden Stufen einer einfachen Pipeline sind IF,ID,EX,MEM und WB. Takte T = Befehle + (Pipestufen - 1) Folgende Abhängigkeiten verhindern, dass die CPI auf eins gehen: Strucual Hazards bzw. Ressourcenkonflikte IF und MEM wollen gleichzeitig auf Speicher lesend oder schreibend zugreifen. Das geht nicht, außer bei Dual-Port-RAM, welcher aber sehr teuer ist. Dieses Problem tritt aber bei modernen CPU's kaum noch auf, da eh intern eine Havard-ähnliche Architektur mit getrenntem Befehls- und Datencache gearbeitet wird. Data Hazards bzw. Datenabhängigkeiten Ein Folgebefehl wartet auf das Writeback der darüber liegenden Pipe, da er von diesem Befehl abhängig ist. Dies kann durch Nops bzw. Stalls ineffizient gelöst werden. Besser der Programmierer oder der Compiler löst diese Abhängigkeiten durch eine clevere Umordnung der Befehlsfolge auf. Es gibt aber noch eine andere Möglichkeit, welche aber hardwareseitig unterstützt werden muss. (VLIW, Superskalar) Forwarding Beim Forwarding werden Ergebnisse, sobald sie vorliegen an die nächste Stufe weitergereicht und nicht erst auf das Write Back gewartet. In anderen Worten: Das Ergebnis der ALU wird dieser sofort wieder eingespeist. Control Hazards bzw. Sprungverzögerungen Sprungergebnisse stehen erst in der Write Back Phase an. Moderne Prozessoren haben aber schon in der Fetch/Decode-Einheit eine Logik, welche die Zieladresse des Sprunges berechnet. Eine andere Möglichkeit ist die des spekulativen Ausführens. Hier tritt aber das Problem auf, dass viel Aufwand bei falscher Spekulation getrieben werden muss. Was ist der Unterschied zwischen echten und unechten Datenabhängigkeiten? Echte Datenabhängigkeiten sind RAW-Konflikte, bei dem ein Befehl auf die Beendigung eines Anderen warten muss, da er das Ergebnis als Operand benötigt. Unechte Datenabhängigkeit sind Abhängigkeiten, welche nur durch Namensabhängigkeit entstehen. Es gibt zwei Arten unechter Datenabhängigkeit: Antidependence sind WAR-Konflikte, welche entstehen, wenn ein Folgebefehl auf ein Register schreiben möchte, das noch von einem Anderen benutzt wird. Output Dependece sind WAW-Konflikte, welche entstehen, wenn mehrere Befehle auf ein und das selbe Register schreiben. Hier muss sichergestellt werden, daß die Schreibreihenfolge der der Befehle entspricht. Beide Abhängigkeiten können durch Register Renaming vermindert werden! Kapitel 7 - Branch Prediction Control Hazards (Jump / Branch Problematik) Sprungbefehle stellen einen Dorn im Auge einer jeden Pipeline dar, da diese besondere Vorkehrungen erfordern. D

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Question

Manycore processor example

[...]

Answer

GPU

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Manycore processor example GPU

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Question

[...]core processor example

GPU

Answer

Many

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Manycore processor example GPU

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Question

[[...]] Compiler must use registers for variables as much as possible

Answer

RISC-V

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[RISC-V] Compiler must use registers for variables as much as possible

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Question

[RISC-V] Compiler must use registers for [...] as much as possible

Answer

variables

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[RISC-V] Compiler must use registers for variables as much as possible

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Question

[RISC-V] Compiler must use [...] for variables as much as possible

Answer

registers

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[RISC-V] Compiler must use registers for variables as much as possible

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Question

[...]core processor
Designed for both parallel and sequential workload with particular focus on low latency and high single-thread performance

Answer

Multi

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Multicore processor Designed for both parallel and sequential workload with particular focus on low latency and high single-thread performance

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Question

Multicore processor
Designed for both [...] and sequential workload with particular focus on low latency and high single-thread performance

Answer

parallel

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Multicore processor Designed for both parallel and sequential workload with particular focus on low latency and high single-thread performance

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Question

Multicore processor
Designed for both parallel and [...] workload with particular focus on low latency and high single-thread performance

Answer

sequential

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Multicore processor Designed for both parallel and sequential workload with particular focus on low latency and high single-thread performance

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Question

Multicore processor
Designed for both parallel and sequential workload with particular focus on [...] and high single-thread performance

Answer

low latency

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Multicore processor Designed for both parallel and sequential workload with particular focus on low latency and high single-thread performance

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Question

Multicore processor
Designed for both parallel and sequential workload with particular focus on low latency and [...]

Answer

high single-thread performance

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Multicore processor Designed for both parallel and sequential workload with particular focus on low latency and high single-thread performance

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Question

Feste Länge String:

// String initializations
[...]
char* str = "constant C-string";

Answer

char name[20] = "BOB";

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// String initializations char name[20] = "BOB"; char* str = "constant C-string";

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Question

Via Pointer / Konstant

// String initializations
char name[20] = "BOB";
[...]

Answer

char* str = "constant C-string";

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// String initializations char name[20] = "BOB"; char* str = "constant C-string";

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Question

[RISC-V] How many core instruction formats are there?

Answer

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RISC-V instructions: Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register numbers, … ➜ 4 core instruction formats (R, I, S, U)

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Question

[RISC-V] The 4 core instruction formats: [...], I, S, U

Answer

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RISC-V instructions: Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register numbers, … ➜ 4 core instruction formats (R, I, S, U)

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Question

[RISC-V] The 4 core instruction formats: R, [...], S, U

Answer

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RISC-V instructions: Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register numbers, … ➜ 4 core instruction formats (R, I, S, U)

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Question

[RISC-V] The 4 core instruction formats: R, I, [...], U

Answer

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RISC-V instructions: Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register numbers, … ➜ 4 core instruction formats (R, I, S, U)

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Question

[RISC-V] The 4 core instruction formats: R, I, S, [...]

Answer

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RISC-V instructions: Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register numbers, … ➜ 4 core instruction formats (R, I, S, U)

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Question

How long are RISC-V instruction words?

Answer

32 bit

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RISC-V instructions: Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register numbers, … ➜ 4 core instruction formats (R, I, S, U)

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Question

How are RISC-V instructions encoded?

Answer

instruction words

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RISC-V instructions: Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register numbers, … ➜ 4 core instruction formats (R, I, S, U)

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Question

What type of programming is required, to make the best use out of Multi- and Manycore processors?

Answer

explicitly parallel programming

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Multi-and manycore processors require explicitly parallel programming

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#has-images

Question

Improving one aspect of computer does not yield

[...] in overall performance

Answer

proportional

improvement

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Improving one aspect of computer does not yield proportional improvement in overall performance

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Tags

#has-images

Answer

Amdahl’s law

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#has-images

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Flashcard 7657787624716

Question

Defining struct point and type [...] for it

typedef struct point Point;
struct point {
    int x;
    int y;
};

Answer

Point

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Defining struct point and type Point for it typedef struct point Point; struct point { int x; int y; };

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Question

Defining [...] and type Point for it

typedef struct point Point;
struct point {
    int x;
    int y;
};

Answer

struct point

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Defining struct point and type Point for it typedef struct point Point; struct point { int x; int y; };

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#has-images

Answer

Full-associative cache

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Flashcard 7657797061900

Question

[...] Total work done per time unit (e.g., tasks / transactions /… per hour)

Answer

Throughput (bandwidth)

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Throughput (bandwidth) Total work done per time unit (e.g., tasks / transactions /… per hour)

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Flashcard 7657798634764

Question

Throughput (bandwidth) [...]

Answer

Total work done per time unit (e.g., tasks / transactions /… per hour)

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Throughput (bandwidth) Total work done per time unit (e.g., tasks / transactions /… per hour)

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Flashcard 7657802042636

Question

[RISC] Arithmetic instructions use [...] operands

Answer

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[RISC] Arithmetic instructions use register operands

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Flashcard 7657803615500

Question

RISC Arithmetic Operators

simple form: one destination, two sources

example: addition

add a, b, c // [...]

Answer

a = b + c

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RISC Arithmetic Operators simple form: one destination, two sources example: addition add a, b, c // a = b + c

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Flashcard 7657807547660

Question

Which endianness has the most-significant byte at the lowest address?

Answer

Big endian

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RISC-V is little endian §Least-significant byte at least address of a word §Big endian: most-significant byte at least address

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Flashcard 7657809120524

Question

Which Byte is at the lowest address in Big endian?

Answer

most-significant

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RISC-V is little endian §Least-significant byte at least address of a word §Big endian: most-significant byte at least address

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Flashcard 7657810693388

Question

[Big endian] At which address is the most significant byte?

Answer

the lowest address

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RISC-V is little endian §Least-significant byte at least address of a word §Big endian: most-significant byte at least address

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Flashcard 7657812266252

Question

[Little endian] Which byte is at the lowest address of a word?

Answer

Least-significant

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RISC-V is little endian §Least-significant byte at least address of a word §Big endian: most-significant byte at least address

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Flashcard 7657813839116

Question

[Little endian] At which address of a word is the least significant byte?

Answer

least

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RISC-V is little endian §Least-significant byte at least address of a word §Big endian: most-significant byte at least address

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Flashcard 7657815411980

Question

Which endianness is RISC-V?

Answer

little endian

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RISC-V is little endian §Least-significant byte at least address of a word §Big endian: most-significant byte at least address

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Flashcard 7657817509132

Question

Physical memory [...] affects latency because Signals have further to travel

Answer

size

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Physical memory size affects latency because Signals have further to travel

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Flashcard 7657819081996

Question

Physical memory size affects [...] because Signals have further to travel

Answer

latency

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Physical memory size affects latency because Signals have further to travel

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Flashcard 7657820654860

Question

Why does physical memory size affect latency?

Answer

because signals have further to travel

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Physical memory size affects latency because Signals have further to travel

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Flashcard 7657823276300

Question

Which bottleneck is also called the von-Neumann-Bottleneck?

Answer

CPU-memory

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CPU-memory bottleneck is also called von-Neumann-Bottleneck

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Question

How is CPU-memory bottleneck also called?

Answer

von-Neumann-Bottleneck

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CPU-memory bottleneck is also called von-Neumann-Bottleneck

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Flashcard 7657827994892

Question

Example: Google data center
Mostly operates at 10% – 50% load
At 100% load less than 1% of the time
➜To improve power efficiency, design processors to
make [...]

Answer

power proportional to load

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Example: Google data center Mostly operates at 10% – 50% load At 100% load less than 1% of the time ➜To improve power efficiency, design processors to make power proportional to load

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Flashcard 7657830092044

Question

Peak performance Performance a computer is guaranteed not to exceed

➜

Not useful for

[...]

Answer

predicting observed performance

(can only be upper limit)

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Peak performance Performance a computer is guaranteed not to exceed ➜ Not useful for predicting observed performance (can only be upper limit)

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Flashcard 7657831664908

Question

Peak performance Performance a computer is guaranteed [...]

➜

Not useful for predicting observed performance

(can only be upper limit)

Answer

not to exceed

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Peak performance Performance a computer is guaranteed not to exceed ➜ Not useful for predicting observed performance (can only be upper limit)

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Flashcard 7657833237772

Question

What's the performance a computer is guaranteed not to exceed?

Answer

Peak performance

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Peak performance Performance a computer is guaranteed not to exceed ➜ Not useful for predicting observed performance (can only be upper limit)

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Flashcard 7657836383500

Question

[...] = Clock cycles / Instruction count

Answer

CPI

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CPI = Clock cycles / Instruction count

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Flashcard 7657837956364

Question

CPI = [...]

Answer

Clock cycles / Instruction count

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CPI = Clock cycles / Instruction count

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Flashcard 7657839529228

Question

CPI = [...] / Instruction count

Answer

Clock cycles

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CPI = Clock cycles / Instruction count

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Flashcard 7657841102092

Question

CPI = Clock cycles / [...]

Answer

Instruction count

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CPI = Clock cycles / Instruction count

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Flashcard 7657846082828

Question

[RISC] [[...]] Used for frequently accessed data

Answer

Registers

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[RISC] [Registers] Used for frequently accessed data

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Flashcard 7657847655692

Question

[RISC] [Registers] Used for [...]

Answer

frequently accessed data

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[RISC] [Registers] Used for frequently accessed data

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Flashcard 7657849228556

Question

[...] = Hit time + Miss rate × Miss penalty

Answer

Average memory access time

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Average memory access time = Hit time + Miss rate × Miss penalty

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Flashcard 7657850801420

Question

Average memory access time = [...] + Miss rate × Miss penalty

Answer

Hit time

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Average memory access time = Hit time + Miss rate × Miss penalty

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Flashcard 7657852374284

Question

Average memory access time = Hit time + [...] × Miss penalty

Answer

Miss rate

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Average memory access time = Hit time + Miss rate × Miss penalty

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Flashcard 7657854209292

Question

Average memory access time = Hit time + Miss rate × [...]

Answer

Miss penalty

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Average memory access time = Hit time + Miss rate × Miss penalty

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Flashcard 7657855782156

Question

Average memory access time = [...]

Answer

Hit time + Miss rate × Miss penalty

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Average memory access time = Hit time + Miss rate × Miss penalty

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Flashcard 7657857879308

Question

Instruction-level parallelism (ILP) (hardware [...]) is hidden from programmer

Answer

executes multiple instructions at once

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Instruction-level parallelism (ILP) (hardware executes multiple instructions at once) is hidden from programmer

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Flashcard 7657859452172

Question

Instruction-level parallelism (ILP) (hardware executes multiple instructions at once) [...]

Answer

is hidden from programmer

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Instruction-level parallelism (ILP) (hardware executes multiple instructions at once) is hidden from programmer

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Flashcard 7657861025036

Question

[...] (hardware executes multiple instructions at once) is hidden from programmer

Answer

Instruction-level parallelism (ILP)

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Instruction-level parallelism (ILP) (hardware executes multiple instructions at once) is hidden from programmer

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Flashcard 7657864432908

Tags

#has-images

Answer

Power for switching a transistor in Watt

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Flashcard 7657870724364

Tags

#has-images

Question

What’s this the formula of?

Answer

Power of switching a transistor in Watts

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Flashcard 7657881472268

Question

[RISC-V] Procedure call: [...] instruction

jal x1, ProcedureLabel

Answer

jump-and-link

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Procedure call instructions Procedure call: jump-and-link instruction jal x1, ProcedureLabel Executed by caller Puts address of instruction after this one in x1 (ra) (return address) Jumps to target address of ProcedureLabel Procedure return:

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Flashcard 7657883045132

Question

[RISC-V] What is the Jump-and-Link function doing?

Answer

Procedure call

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Question

[RISC-V] Who is Jump-and-Link (jal) executed by?

Answer

the procedure caller

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Flashcard 7657886190860

Question

[RISC-V] Which address is put into the Return address (ra) by Jump-and-Link (jal)?

Answer

the instruction immediately after it

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Flashcard 7657887763724

Question

Which target address does this jump to?

jal x1, ProcedureLabel

Answer

ProcedureLabel

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nstructions Procedure call: jump-and-link instruction jal x1, ProcedureLabel Executed by caller Puts address of instruction after this one in x1 (ra) (return address) Jumps to target address of ProcedureLabel Procedure return: jump-and-link register instruction jalr x0, 0(x1) Executed by callee Like jal, but jumps to 0 + address in x1 (ra) No return address (x0 cannot be changed) Can also be

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Flashcard 7657889336588

Question

What is the jump-and-link register (jalr) instruction procedurally?

Answer

Procedure return

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cedure call: jump-and-link instruction jal x1, ProcedureLabel Executed by caller Puts address of instruction after this one in x1 (ra) (return address) Jumps to target address of ProcedureLabel Procedure return: jump-and-link register instruction jalr x0, 0(x1) Executed by callee Like jal, but jumps to 0 + address in x1 (ra) No return address (x0 cannot be changed) Can also be used for uncondi

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Flashcard 7657890909452

Question

[RISC-V] What's the equivalent instruction to a procedure return?

Answer

jump-and-link register (jalr)

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and-link instruction jal x1, ProcedureLabel Executed by caller Puts address of instruction after this one in x1 (ra) (return address) Jumps to target address of ProcedureLabel Procedure return: jump-and-link register instruction jalr x0, 0(x1) Executed by callee Like jal, but jumps to 0 + address in x1 (ra) No return address (x0 cannot be changed) Can also be used for unconditional jumps </

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Flashcard 7657892482316

Question

Who is jump-and-link register (jalr) executed by?

Answer

called procedure (callee)

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Puts address of instruction after this one in x1 (ra) (return address) Jumps to target address of ProcedureLabel Procedure return: jump-and-link register instruction jalr x0, 0(x1) Executed by callee Like jal, but jumps to 0 + address in x1 (ra) No return address (x0 cannot be changed) Can also be used for unconditional jumps

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Flashcard 7657894055180

Question

Where does this jump to?

jalr x0, 0(x1)

Answer

0 + address in x1 (ra)

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fter this one in x1 (ra) (return address) Jumps to target address of ProcedureLabel Procedure return: jump-and-link register instruction jalr x0, 0(x1) Executed by callee Like jal, but jumps to 0 + address in x1 (ra) No return address (x0 cannot be changed) Can also be used for unconditional jumps

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Flashcard 7657895628044

Question

What's the return address of jump-and-link register (jalr)?

Answer

x0 / zero -> it doesn't have a return address

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) (return address) Jumps to target address of ProcedureLabel Procedure return: jump-and-link register instruction jalr x0, 0(x1) Executed by callee Like jal, but jumps to 0 + address in x1 (ra) No return address (x0 cannot be changed) Can also be used for unconditional jumps

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Flashcard 7657897200908

Question

What can jump-and-link register (jalr) also be used for, if not procedure returns?

Answer

unconditional jumps

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rocedure return: jump-and-link register instruction jalr x0, 0(x1) Executed by callee Like jal, but jumps to 0 + address in x1 (ra) No return address (x0 cannot be changed) Can also be used for unconditional jumps

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Flashcard 7657899035916

Question

RISC-V does [...] require word alignment in memory

Answer

not

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RISC-V does not require word alignment in memory

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Flashcard 7657900608780

Question

RISC-V does not require [...] alignment in memory

Answer

word

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RISC-V does not require word alignment in memory

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Flashcard 7657902181644

Question

RISC-V does not require word alignment in [...]

Answer

memory

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RISC-V does not require word alignment in memory

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Edited, memorised or added to reading queue

on 21-Sep-2024 (Sat)

pdf

pdf

pdf

pdf

Procedure call instructions

pdf

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Multicore

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Memory operands

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Sign extension

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From clock cycles to instruction count and CPI

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From clock cycles to instruction count and CPI

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Passing arrays as parameters